`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/28 11:37:54
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top
(
    //sim_adc_clk
    input           adc_ref_clk     ,
    //ddr4
    input           ddr4_diff_clk_n ,
    input           ddr4_diff_clk_p ,
    output          C0_DDR4_act_n   ,
    output [16:0]   C0_DDR4_adr     ,
    output [1:0]    C0_DDR4_ba      ,
    output [0:0]    C0_DDR4_bg      ,
    output [0:0]    C0_DDR4_ck_c    ,
    output [0:0]    C0_DDR4_ck_t    ,
    output [0:0]    C0_DDR4_cke     ,
    output [0:0]    C0_DDR4_cs_n    ,
    inout  [7:0]    C0_DDR4_dm_n    ,
    inout  [63:0]   C0_DDR4_dq      ,
    inout  [7:0]    C0_DDR4_dqs_c   ,
    inout  [7:0]    C0_DDR4_dqs_t   ,
    output [0:0]    C0_DDR4_odt     ,
    output          C0_DDR4_reset_n ,
    output          ddr4_done_led   ,
    //pcie
    input  [0:0]    pcie_diff_clk_n ,
    input  [0:0]    pcie_diff_clk_p ,
    input  [7:0]    pcie_mgt_rxn    ,
    input  [7:0]    pcie_mgt_rxp    ,
    output [7:0]    pcie_mgt_txn    ,
    output [7:0]    pcie_mgt_txp    ,
    input           pcie_resetn     ,
    output          pcie_done_led   

);

//wire define
//ui_clk
wire        ui_clk              ;
wire        peripheral_aresetn  ;
//pcie_peripheral
wire [31:0] key_tri_i           ;
wire [31:0] led_tri_o           ;
//dbuf
wire        ud_wclk             ;
wire [63:0] ud_wdata            ;
wire        ud_wde              ;
wire        ud_wfifo_rst        ;
wire        ud_wvs              ;
wire        ud_wvs_clk          ;
wire        ud_wfull            ;
wire [7:0]  wbuf_sync_o         ;
wire        fdma_wirq           ;

wire        Tti_wirq            ;
wire        Tri_pluse_start     ;
wire        Tri_pluse_stop      ;
//sim_data
wire [15:0] adc_sim_data        ;
wire        adc_sim_data_vaild  ;
wire        adc_data_clk        ;
wire        adc_data_rstn       ;

clk_wiz_0 clk_wiz_0
(
    .clk_out1           (adc_data_clk       ),     
    .locked             (adc_data_rstn      ),       
    .clk_in1            (adc_ref_clk        )      
);

data_sim data_sim_i
(
    .data_clk           (adc_data_clk       ),
    .data_rstn          (adc_data_rstn      ),
        
    .data_out           (adc_sim_data       ),
    .data_vaild         (adc_sim_data_vaild )   
);


dbuf_ctrl #(
    .DATA_WIDTH ( 64 ))
 u_dbuf_ctrl (
    .adc_data_clk       ( adc_data_clk        ),
    .adc_data_rstn      ( adc_data_rstn       ),
    .adc_data_all       ( {adc_sim_data,
                          adc_sim_data,
                          adc_sim_data,
                          adc_sim_data}       ),
    .adc_wvs_clk        ( adc_data_clk        ),
    .Tri_pluse_start    ( Tri_pluse_start     ),
    .Tri_pluse_stop     ( Tri_pluse_stop      ),
    .Tri_pluse_clk      ( adc_data_clk        ),

    .ud_wclk            ( ud_wclk             ),
    .ud_wdata           ( ud_wdata            ),
    .ud_wde             ( ud_wde              ),
    .ud_wfifo_rst       ( ud_wfifo_rst        ),
    .ud_wvs             ( ud_wvs              ),
    .ud_wvs_clk         ( ud_wvs_clk          ),
    .ud_wfull           ( ud_wfull            ),
    .fdma_wirq          ( fdma_wirq           )
);

Tri2pc_gen #(
    .LAST_TIME ( 32'd10 ))
 u_Tri2pc_gen (
    .clk                ( ui_clk              ),
    .rstn               ( peripheral_aresetn  ),
    .fdma_wirq          ( fdma_wirq           ),
    .wbuf_sync          ( wbuf_sync_o         ),

    .Tti_wirq           ( Tti_wirq            ) 
);

system_wrapper system_wrapper_i
(
    //ddr4
    .C0_DDR4_act_n      (C0_DDR4_act_n      ),
    .C0_DDR4_adr        (C0_DDR4_adr        ),
    .C0_DDR4_ba         (C0_DDR4_ba         ),
    .C0_DDR4_bg         (C0_DDR4_bg         ),
    .C0_DDR4_ck_c       (C0_DDR4_ck_c       ),
    .C0_DDR4_ck_t       (C0_DDR4_ck_t       ),
    .C0_DDR4_cke        (C0_DDR4_cke        ),
    .C0_DDR4_cs_n       (C0_DDR4_cs_n       ),
    .C0_DDR4_dm_n       (C0_DDR4_dm_n       ),
    .C0_DDR4_dq         (C0_DDR4_dq         ),
    .C0_DDR4_dqs_c      (C0_DDR4_dqs_c      ),
    .C0_DDR4_dqs_t      (C0_DDR4_dqs_t      ),
    .C0_DDR4_odt        (C0_DDR4_odt        ),
    .C0_DDR4_reset_n    (C0_DDR4_reset_n    ),
    .ddr4_diff_clk_n    (ddr4_diff_clk_n    ),
    .ddr4_diff_clk_p    (ddr4_diff_clk_p    ),
    .ddr4_done_led      (ddr4_done_led      ),
    .ui_clk             (ui_clk             ),
    .peripheral_aresetn (peripheral_aresetn ),
    //pcie
    .pcie_diff_clk_n    (pcie_diff_clk_n    ),
    .pcie_diff_clk_p    (pcie_diff_clk_p    ),
    .pcie_done_led      (pcie_done_led      ),
    .pcie_mgt_rxn       (pcie_mgt_rxn       ),
    .pcie_mgt_rxp       (pcie_mgt_rxp       ),
    .pcie_mgt_txn       (pcie_mgt_txn       ),
    .pcie_mgt_txp       (pcie_mgt_txp       ),
    .pcie_resetn        (pcie_resetn        ),
    .key_tri_i          (key_tri_i          ),
    .led_tri_o          (led_tri_o          ),
    //dbuf
    .ud_wclk            (ud_wclk            ),
    .ud_wdata           (ud_wdata           ),
    .ud_wde             (ud_wde             ),
    .ud_wfifo_rst       (ud_wfifo_rst       ),
    .ud_wvs             (ud_wvs             ),
    .ud_wvs_clk         (ud_wvs_clk         ),
    .ud_wfull           (ud_wfull           ),
    .wbuf_sync_o        (wbuf_sync_o        ),
    .fdma_wirq          (fdma_wirq          )
);
    
vio_0 vio_0 (
   .clk                 (adc_data_clk       ), 
   .probe_out0          (Tri_pluse_start    ),
   .probe_out1          (Tri_pluse_stop     )
);


endmodule
